SRAM vs DRAM: The Speed-Density Trade-Off Behind All Modern Memory
SRAM (Static RAM) uses six transistors per bit and holds data without refresh — fast but large and expensive. DRAM (Dynamic RAM) uses one transistor and one capacitor per bit — dense and cheap but requires constant refresh because capacitors leak charge. This fundamental trade-off is why CPUs use SRAM for caches (small, fast, expensive) and DRAM for main memory (large, slower, cheap). The DRAM refresh requirement creates the latency stalls that techniques like Tail Slayer are designed to mitigate.
All modern computer memory is built on a fundamental trade-off between two technologies: SRAM (Static Random-Access Memory) and DRAM (Dynamic Random-Access Memory). They store the same thing — binary data — but use different physical mechanisms with dramatically different performance characteristics. ## SRAM: Fast but Large SRAM stores each bit using six transistors arranged in a cross-coupled flip-flop configuration. As long as power is supplied, the flip-flop holds its state indefinitely — no refresh needed. SRAM is fast (sub-nanosecond access times), deterministic (no refresh stalls), but physically large (six transistors per bit) and expensive per bit. SRAM is used for CPU cache memory (L1, L2, L3) where speed is critical and capacity requirements are small (kilobytes to tens of megabytes). ## DRAM: Dense but Needs Refresh DRAM stores each bit as charge on a single tiny capacitor, controlled by one transistor — Bob Dennard's 1960s invention at IBM. One transistor plus one capacitor per bit means DRAM is roughly 6x denser than SRAM per unit area, making it dramatically cheaper per gigabyte. The trade-off: capacitors leak charge. Every ~3.9 microseconds (per the JEDEC specification), the memory controller must pause to recharge all cells — the TRFC (refresh cycle time) stall. During refresh, that memory region is inaccessible for ~400-500 nanoseconds. This is normally invisible to software but creates unpredictable latency spikes in ultra-low-latency applications. ## The Hierarchy Modern computers use both in a layered hierarchy: | Level | Technology | Capacity | Access Time | |-------|-----------|----------|-------------| | L1 Cache | SRAM | 32-128 KB | ~1 ns | | L2 Cache | SRAM | 256 KB - 1 MB | ~3-5 ns | | L3 Cache | SRAM | 4-128 MB | ~10-20 ns | | Main Memory | DRAM (DDR5) | 8-512 GB | ~80 ns (normal), ~400+ ns (during refresh) | Data frequently accessed stays in SRAM caches; the bulk of working data lives in DRAM. Cache hit rates above 95% mean most memory accesses never reach DRAM — but the ones that do are subject to the refresh latency penalty. Tail Slayer: Hedging DRAM Refresh Latency for Sub-Microsecond Reads Rowhammer: The DRAM Vulnerability That Flips Bits by Reading Memory