Semiconductor Fabrication: Turning Sand Into Chips at Atomic Scale

Semiconductor fabrication is the multi-step process that turns a polished silicon wafer into hundreds of patterned dies, each containing billions of transistors. A leading-edge process flow at a node like 5 nm or 3 nm involves more than 1,000 individual steps and takes roughly three months from wafer start to packaged die. Key step families include photolithography (projecting circuit patterns through reticles using deep-UV or extreme ultraviolet light), wet and dry etching (selectively removing material), ion implantation and diffusion (introducing dopants to define transistor regions), chemical vapor deposition and atomic layer deposition (growing thin films of metal or dielectric), and chemical mechanical polishing (planarizing the wafer between layers). Front-end-of-line (FEOL) builds the transistors; back-end-of-line (BEOL) wires them up with many copper interconnect layers. Wafers then move to packaging (dicing, bonding, encapsulation, and increasingly 2.5D/3D advanced packaging with substrates like CoWoS). Fabs are extraordinary infrastructure: a single leading-edge facility costs $15-25 billion, operates a Class 1 or Class 10 cleanroom, draws tens of thousands of cubic metres of ultrapure water per day, uses thousands of process chemicals (many of them PFAS), and consumes hundreds of megawatts of electricity continuously. The big three leading-edge foundries are TSMC, Samsung Foundry, and Intel. Yield, the fraction of dies that pass test, is a closely guarded competitive metric because it directly drives effective cost per die.