NAND Flash Endurance: P/E Cycles, Cell Types, and Wear Leveling

Flash memory cells wear out: every program/erase cycle (P/E cycle) slightly degrades the oxide layer that traps charge, until the cell can no longer hold data reliably. Endurance depends primarily on how many bits each cell stores: SLC (1 bit) endures roughly 50,000–100,000 P/E cycles; MLC (2 bits) about 3,000–10,000; TLC (3 bits) about 500–5,000 in consumer parts (up to ~10,000 for screened industrial 3D TLC); QLC (4 bits) about 100–1,000. Fewer bits per cell means wider voltage margins and more wear tolerance. pSLC mode runs MLC/TLC as one bit per cell, trading capacity for near-SLC endurance — a common trick in industrial cards. Wear leveling is the controller-side answer: remapping logical blocks across physical flash so no single block wears out early. Early SD-card controllers barely did this, mapping addresses close to statically — which is why running an OS off old cards killed them quickly: constantly-rewritten state and log files hammered a handful of physical blocks while the rest of the card sat fresh. Modern cards and SSDs all shuffle; the quality of wear leveling, spare-block provisioning, and error correction is why two products built on the same NAND type can carry very different TBW ratings. In practice endurance is quoted as TBW (terabytes written) or, for industrial parts, as rated P/E cycles in a datasheet. Empirically, industrial-grade microSD cards outlast consumer ones by roughly an order of magnitude (see microSD endurance test).